Memory devices can be classified as two broad categories, volatile memories such as static random-access memory (SRAM) as well as dynamic random-access memory (DRAM) and non-volatile memories (NVMs) such as Flash, resistive random-access memory (RRAM), magnetoresistance random-access memory (MRAM) as well as phase change random-access memory (PCRAM) etc. The volatile memories lose the data when the power is turned off. In contrast, the non-volatile memories retain the stored data even when the power is turned off.
MRAM is a new type of non-volatile memory that utilizes the magnetic polarization of the ferromagnetic materials of the magnetic tunneling junction (MTJ) instead of electrical charges to store information. The MTJ normally includes three layers, i.e. the reference layer which has a fixed magnetic polarization, the free layer which has a programmable magnetic polarization and the non-ferromagnetic tunneling layer in between of the reference layer and the free layer. If the magnetic polarization of the free layer is in the parallel direction as that of the reference layer, the MTJ has resistance RP and the MRAM device stores 1 bit data of ‘0’. If the magnetic polarization of the free layer is in the anti-parallel direction as that of the reference layer, the MTJ resistance is RAP (RAP>RP) and the MRAM device stores 1 bit data of ‘1’. The tunneling magnetoresistance (TMR) ratio, (RAP−RP)/RP, indicates the gap between the two resistance states of an MTJ.
In particular, spin-torque-transfer (STT) MRAM uses the flow of spin-polarized electrons that fulfills a critical current density to directly change the polarization of the free layer. The state of the MTJ depends on the direction of electron flow. Reading the state of the MTJ uses a current smaller than the critical current to avoid unnecessary write to the MTJ.
FIG. 1 is a schematic 100 illustrating the causes that contribute to the failure of NVM chips. The condition of the silicon NVM chip 102 may be attributable to complementary metal oxide semiconductor (CMOS) circuit performance 104 and the NVM device (i.e. memory element) performance 106. In the event of a faulty chip, it is very important to be able to find the root of the failure and optimize the design in future fabrication. While testing methods for CMOS circuits in a complex system have been well established, the characterization method for NVM devices (memory elements in NVM) remains relatively unexplored.
The series resistance along a data path of a NVM device may include the resistance of the memory element (e.g. the MTJ), the resistance of a selection component, resistances of other components such as column switches as well as parasitic resistances. These resistances of the selection component and other components as well as parasitic resistances may be comparable to the resistance of the memory element. As the CMOS technology scales, the large process variations hinder the accurate characterization of the resistance of the memory element in a NVM memory array. It is necessary to have a method that measures the resistances of the memory element of both states in a NVM memory array that has strong tolerance to CMOS process variation and parasitic effects in order to facilitate statistical analysis of the resistance distribution for improving the back-end-of-the-line (BEOL) NVM process.